Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of application U.S. Ser. No. 12/274,804,filed Nov. 20, 2008, and is based and claims the benefit of priorityfrom the prior Japanese Patent Application 2007-314729, filed on Dec. 5,2007, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Field

An aspect of the embodiments discussed herein is directed to asemiconductor device having a multilayer wiring structure and a methodof manufacturing such a semiconductor device.

2. Description of the Related Art

Semiconductor integrated circuits manufactured today each contain vastnumbers of semiconductor elements on the common board thereof and employa multilayer wiring structure to connect such semiconductor elementswith each other.

In a multilayer wiring structure, interlayer insulating films, in eachof which wiring patterns are embedded to form a wiring layer, arelaminated, and via contacts formed inside the interlayer insulatingfilms connect the upper wiring layer and the lower wiring layer.

In particular, in current ultrafine and ultrahigh-speed semiconductordevices, low-dielectric-constant films (so-called low-k films) are usedas such interlayer insulating films to reduce the problem of signaldelay, for example RC delay, that occurs in a multilayer wiringstructure, as well as low-resistance copper (Cu) patterns used as wiringpatterns.

In this type of multilayer wiring structure, in which Cu wiring patternsare embedded in interlayer insulating films with a low dielectricconstant, it is desirable to pattern the Cu layer by dry etching. Amethod often used to pattern the Cu layer by dry etching is a so-calleddamascene or dual damascene process, wherein wiring trenches or viaholes are carved through interlayer insulating films in advance. Thesewiring trenches or via holes are filled with a Cu layer and thenunnecessary portions of the Cu layer remaining on the interlayerinsulating films are removed by chemical mechanical polishing (CMP).

Any direct contact of a Cu wiring pattern with an interlayer insulatingfilm in this process would cause Cu atoms to diffuse into the interlayerinsulating film, thereby leading to short circuits or other defects.These short circuits or other defects are generally avoided by coveringthe side walls and bottoms of wiring trenches or via holes used to formCu wiring patterns with conductive diffusion barriers, also known asbarrier metal films, and then coating the barrier metal films with a Culayer. Examples of materials used for such a barrier metal film mayinclude a high-melting-point metal such as tantalum (Ta), titanium (Ti),and tungsten (W) as well as conductive nitrides thereof.

However, in ultrafine and ultrahigh-speed semiconductor device based oncurrent 45-nm technology or newer technologies, the size of wiringtrenches or via holes carved through interlayer insulating films issignificantly reduced along with miniaturization. To achieve desirablereduction in the resistance of wiring while using such ahigh-dielectric-constant barrier metal film, it is accordingly necessarythat each of barrier metal films covering such ultrafine wiring trenchesor via holes is as thin as possible while seamlessly covering the sidewalls and bottoms of the wiring trenches or via holes.

A technique that has been proposed to address this situation is directcovering of wiring trenches or via holes carved through interlayerinsulating films with a copper-manganese alloy layer (Cu—Mn alloylayer). In this technique, Mn atoms contained in a Cu—Mn alloy layerreact with Si and oxygen atoms contained in an interlayer insulatingfilm and thus a manganese-silicon oxide layer having a thickness in therange of 2 nm to 3 nm and a composition of MnSi_(x)O_(y) is formedinside the Cu—Mn alloy layer as a diffusion barrier film.

However, it is known that in this technique the internally formedmanganese-silicon oxide layer contains manganese (Mn) at a too lowconcentration and thus the adhesion of that layer to a Cu film isproblematically weak.

Consequently, another structure of a barrier metal film in which a Cu—Mnalloy layer is combined with a barrier metal film based on ahigh-melting-point metal such as Ta or Ti has been proposed.

Such a barrier metal structure combining a Cu—Mn alloy layer with abarrier metal film based on a high-melting-point metal such as Ta or Tiprovides preferable characteristics with improved resistance tooxidation through the sequence described below.

Recently, use of low-dielectric-constant porous films as alow-dielectric constant material constituting interlayer insulatingfilms has been proposed to prevent signal delay, for example RC delay.However, unfortunately, such a low-dielectric-constant porous materialhas a low density and thus is likely to be damaged by plasma during themanufacturing process, and a damaged film often retains moisture on thesurface and inside thereof. Accordingly, a barrier metal film formed onsuch a low-dielectric-constant porous film would be likely to beoxidized by moisture retained inside and this often results indeteriorated characteristics of the barrier metal film and poor adhesionthereof to a Cu wiring layer or a via plug.

On the other hand, the Cu—Mn alloy layer described above contains Mnatoms, and if the layer is used as a seed layer, these Mn atoms reactwith oxidized portions of a barrier metal film, thereby ensuringcharacteristics of the barrier metal film necessary for its use as adiffusion barrier and maintaining high adhesion thereof to a Cu wiringlayer or a via plug.

Related information may be found in the following patent documents:Patent Document 1: Japanese Laid-open Patent Publication No.2007-142236; Patent Document 2: Japanese Laid-open Patent PublicationNo. 2005-277390.

SUMMARY

According to an aspect of an embodiment, a semiconductor device has afirst insulating film formed over a semiconductor substrate, a firstopening formed in the first insulating film, a first manganese oxidefilm formed along an inner wall of the first opening, a first copperwiring embedded in the first opening, and a second manganese oxide filmformed on the first copper wiring containing carbon.

These together with other aspects and advantages which will besubsequently apparent, reside in the details of construction andoperation as more fully hereinafter described and claimed, referencebeing had to the accompanying drawings forming a part hereof, whereinlike numerals refer to like parts throughout.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1F are diagrams for explanation of the conventional art;

FIG. 2 is a diagram for explanation of a problem in the conventionalart;

FIGS. 3A-3F are diagrams for explanation of another conventional art;

FIG. 4 is a diagram illustrating a configuration of a semiconductordevice according to Embodiment 1;

FIGS. 5A-5L are diagrams illustrating a manufacturing process of thesemiconductor device according to Embodiment 1;

FIG. 6 is a diagram for explanation of reaction that occurs in a processaccording to Embodiment 1;

FIG. 7 is a diagram for explanation of the advantageous effect ofEmbodiments 1 and 2;

FIG. 8A is a diagram illustrating a configuration of a standard devicetested as a control to demonstrate the advantageous effect of Embodiment1;

FIG. 8B is a diagram illustrating a configuration of a device used todemonstrate the advantageous effect of Embodiment 1;

FIGS. 9A-9K are diagrams illustrating a manufacturing process of asemiconductor device according to Embodiment 2;

FIG. 10 is a diagram illustrating a configuration of a device used todemonstrate the advantageous effect of Embodiment 2;

FIG. 11 is an additional diagram demonstrating the advantageous effectof Embodiment 2; and

FIG. 12 is a diagram illustrating a configuration of a device used todemonstrate the advantageous effect of Embodiment 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A to 1F are diagrams representing the process of forming a Cuwiring pattern.

In FIG. 1A, a silicon dioxide film 12 consisting of a methylsilsesquioxane (MSQ) film covers an insulating film 11 formed on asilicon substrate not shown in the drawing.

Then, as shown in FIG. 1B, a wiring trench 12T corresponding to adesired wiring pattern is carved through the silicon dioxide film 12.

After that, as shown in FIG. 1C, a barrier metal film 13BM consisting ofa high-melting-point metal, such as Ta, or a conductive nitride thereof,such as TaN, TiN, or WN, is formed so as to coat the top of the silicondioxide film 12 and the side walls and bottom of the wiring trench 12T.

In this structure shown in FIG. 1C, a Cu—Mn alloy layer 13CM is alsoformed on the barrier metal film 13BM so as to have the cross-sectionalshape fitting the barrier metal film 13BM.

Furthermore, a Cu layer 13 is formed on the Cu—Mn alloy layer 13CM so asto fill the wiring trench 12T as shown in FIG. 1C.

Then, CMP is applied to shave the Cu layer 13, the Cu—Mn alloy layer13CM and the barrier metal film 13BM existing therebeneath until thesurface of the silicon dioxide film 12 is exposed. This step results inthe structure shown in FIG. 1D, wherein the wiring trench 12T is filledwith a Cu wiring pattern 13P.

After that, as shown in FIG. 1E, another silicon dioxide film 14consisting of an MSQ film is formed on the structure shown in FIG. 1D,and the structure shown in FIG. 1E is then heated at a giventemperature, for example, 400° C. to provide the structure shown in FIG.1F. As a result, Ms atoms contained in the Cu—Mn alloy layer 13CM aretransported to the surface of the Cu wiring pattern 13P, and thetransported Mn atoms react with oxygen and Si atoms existing in thesilicon dioxide film 14, thereby forming a manganese oxide film 13MOxhaving a composition of MnSi_(x)O_(y) on the surface of the Cu wiringpattern 13P.

This process may exclude the use of a SiN film or other kinds of etchingstopper films with a high dielectric constant, which is placed betweenthe insulating films 12 and 14 in a known method, and is expected tofurther reduce the parasitic capacitance of the Cu wiring pattern 13P.

It should be noted that the Cu—Mn alloy layer 13CM existing between theCu wiring pattern 13P and the barrier metal film 13BM releases Mn atomsand this transportation of Mn atoms completely blurs the boundarybetween the Cu—Mn alloy layer 13CM and the Cu wiring pattern 13P.

The wiring structure containing the Cu wiring pattern 13P shown in FIG.1F may have an insufficient performance of the manganese oxide film13MOx as a diffusion barrier. For example, Cu wiring patterns 13P formedside-by-side as shown in FIG. 2 could possibly generate a potentialdifference between themselves so that Cu ions released from one Cuwiring pattern 13P1 would diffuse into the other Cu wiring pattern 13P2,thereby leading to a short circuit.

However, surfaces of the Cu wiring patterns 13P1 and 13P2 other than thetop surfaces are coated with a barrier metal film 13BM and thusdiffusion of Cu atoms therefrom may be prevented.

In addition, These discusses a technique to make up for the insufficientperformance of the above-mentioned manganese oxide film 13MOx as adiffusion barrier by covering the manganese oxide film 13MOx with abarrier film such as a SiCN film as shown in FIGS. 3A to 3D. It shouldbe noted that the components in FIGS. 3A to 3D that have already beendescribed above are numbered with the reference numerals used in theprevious explanation to avoid repetition.

The structure illustrated in FIG. 3A is equivalent to that shown in FIG.1D and thus formed through the steps described by FIGS. 1A to 1C. InFIG. 3B, a silicon dioxide film 15 having a composition identical orsimilar to that of the silicon dioxide film 12 described earlier isformed on the structure shown in FIG. 3A. Then, this structure is heatedat a temperature of approximately 400° C. to form a manganese oxide film13MOx covering the surface of the Cu wiring pattern 13P describedearlier in the same manner as shown in FIG. 1F.

After that, as shown in FIG. 3C, the silicon dioxide film 15 and aportion of the silicon dioxide film 12 lying therebeneath are removed bywet etching or plasma etching until the manganese oxide film 13MOx isexposed.

In this step, it is difficult to stop the wet etching or plasma etchingjust at the time of the exposure of the manganese dioxide film 13MOx.Exposing the entire surface of the manganese oxide film 13MOx requiresexcessive etching. Therefore, in the structure shown in FIG. 3C, theupper part of the Cu wiring pattern 13P supporting the manganese oxidefilm 13MOx is also exposed so as to protrude from the insulating film12.

Then, as shown in FIG. 3D, a diffusion barrier film 16 consisting of aSiCN film is formed on the silicon dioxide film 12 so as to cover theprotruding upper part of the Cu wiring pattern 13P in FIG. 3C.Thereafter, the next insulating film 17 is formed on this diffusionbarrier film 16 as shown in FIG. 3E.

It should be noted that the upper part of the Cu wiring pattern 13Pprotrudes from the surface of the insulating film 12 as shown in FIG. 3Dand accordingly the diffusion barrier film 16 has a protrusion 16P. Thiscauses the insulating film 17 to have a protrusion 17P as shown in FIG.3E.

After that, the damascene process is applied to the inside of theinsulating film 17 in the same manner as described earlier to form a Cuwiring pattern 18P that is supported by a barrier metal film 18BM and iscoated with a manganese oxide film 19 as shown in FIG. 3F.

However, in such a structure, each upper Cu wiring pattern 18P extendsso as to cross over the bumps made by the lower Cu wiring patterns 13P.This makes it likely that the upper Cu wiring patterns 18P and the lowerCu wiring patterns 13P become short-circuited.

FIG. 4 is a diagram illustrating a configuration of a semiconductordevice according to Embodiment 1, and FIGS. 5A to 5M and FIG. 6 arediagrams illustrating a manufacturing process of the semiconductordevice.

In FIG. 4, element regions 41A and 41B are defined on a siliconsubstrate 41 by element-isolating structures 411. On the element region41A, a gate insulating film 42A is positioned on the silicon substrate41 and a gate electrode 43A made of polysilicon or the like is formedthereon, whereas on the element region 41B, a gate insulating film 42Bis positioned on the silicon substrate 41 and a gate electrode 43B madeof polysilicon or the like is formed thereon.

The gate electrode 43A has side walls coated with insulating films and,at both sides of this gate electrode 43A, diffusion regions 41 a and 41b are formed by ion implantation in the element region 41A of thesilicon substrate 41. Similarly, the gate electrode 43B also has sidewalls coated with insulating films and, at both sides of this gateelectrode 43B, diffusion regions 41 c and 41 d are formed by ionimplantation in the element region 41B of the silicon substrate 41. As aresult, transistors Tr1 and Tr2 are formed in the element regions 41Aand 41B, respectively.

The gate electrodes 43A and 43B are covered with an insulating film 43formed on the silicon substrate 41, and a multilayer wiring structure 20is formed on this insulating film 43. This multilayer wiring structure20 will be detailed below.

As shown in FIG. 4, the multilayer wiring structure 20 has a so-calledlow-k interlayer insulating film 22 formed on the insulating film 43.Examples of this low-k interlayer insulating film 22 may include an MSQfilm with a dielectric constant of 2.6, a hydrocarbon polymer film suchas SiLK or Porous SiLK (registered trademarks of The Dow ChemicalCompany), and a SiOC film produced by plasma chemical vapor deposition(CVD).

The interlayer insulating film 22 is coated with a carbon-includinginsulating film 24 that contains carbon (C) and silicon (Si), has athickness in the range of 15 nm to 30 nm, and preferably consisting of aSiC film or a SiCN film. As described later, this carbon—includinginsulating film 24 further includes oxygen (O).

On the carbon-including insulating film 24, a low-k interlayerinsulating film 25 equivalent to the above-mentioned low-k interlayerinsulating film 22 is formed so as to have a thickness, for example, inthe range of 250 nm to 300 nm. This low-k interlayer insulating film 25is coated with a carbon (as well as silicon and oxygen)—includinginsulating film 27 that is equivalent to the above-mentionedcarbon-including insulating film 24 and has a thickness in the range of15 nm to 30 nm.

Furthermore, on the carbon-including insulating film 27, a low-kinterlayer insulating film 28 equivalent to the above-mentioned low-kinterlayer insulating films 22 and 25 is formed so as to have athickness, for example, in the range of 250 nm to 300 nm. This low-kinterlayer insulating film 28 is also coated with a carbon (as well assilicon and oxygen)—including insulating film 30 that is equivalent tothe above-mentioned carbon-including insulating films 24 and 27 and hasa thickness in the range of 15 nm to 30 nm.

Through the interlayer insulating film 22, wiring trenches 22T1 and 22T2are carved, which are filled with Cu wiring patterns 23P and 23Q,respectively. Side walls of these wiring trenches 22T1 and 22T2 are eachcoated with a barrier metal film 23BM consisting of a high-melting-pointmetal such as Ta, Ti, or W, or a conductive nitride thereof such as TaN,TiN, or WN. Strictly speaking, the adjective “metal” may not be used todescribe a barrier metal film 23BM consisting of a conductive nitride.However, in the present embodiment, such a barrier film is also referredto as “a barrier metal film” in accordance with established practice.Meanwhile, the top of the Cu wiring pattern 23P is covered with amanganese oxide film 23MOx that includes carbon, has a composition ofMnSi_(x)O_(y)C_(z) (x=0.3 to 1.0; y=0.75 to 3.0; z=0.2 to 0.7), andformed along the carbon-including insulating film 24 so as to have athickness approximately in the range of 1 nm to 5 nm. Such a manganeseoxide film 23MOx is also formed on the top of the Cu wiring pattern 23Q.A more detailed description of this manganese oxide film 23MOx will beprovided later.

As described later, the boundary between the Cu wiring pattern 23P andthe barrier metal film 23BM consists of a manganese oxide film 23MOyformed so as to have a thickness in the range of 1 nm to 5 nm and acomposition different from that of the manganese oxide film 23MOx. Thismanganese oxide film 23MOy includes no or little carbon and Si, and theconcentrations of these elements included therein are substantiallylower than those in the manganese oxide film 23MOx, if any. For example,the manganese oxide film 23MOy has a composition of MnO_(p)C_(q) (p=0.5to 1.5; q=0.01 to 0.05; q<z).

Through the interlayer insulating film 25, wiring trenches 25T1, 25T2,and 25T3 are carved, and these wiring trenches 25T1, 25T2, and 25T3 arefilled with Cu wiring patterns 26P, 26Q, and 26R, respectively. Thelower part of the Cu wiring pattern 26P forms a Cu via plug 26V, whichextends through the manganese oxide film 23MOx to make an electricalcontact with the Cu wiring pattern 23P.

The side walls of the wiring trenches 25T1, 25T2, and 25T3 are eachcoated with a barrier metal film 26BM equivalent to the barrier metalfilm 23BM. On the top of the Cu wiring pattern 26P, a manganese oxidefilm 26MOx equivalent to the manganese oxide film 23MOx is formed alongthe carbon-including insulating film 27 so as to have a thicknessapproximately in the range of 1 nm to 5 nm. Such a manganese oxide film26MOx is also formed on the top of the Cu wiring patterns 26Q and 26R.

The boundary between the Cu wiring pattern 26P and the barrier metalfilm 26BM consists of a manganese oxide film 26MOy that is equivalent tothe manganese oxide film 23MOy and formed so as to have a thickness inthe range of 1 nm to 5 nm.

Through the interlayer insulating film 28, wiring trenches 28T1 and 28T2are carved, and these wiring trenches 28T1 and 28T2 are filled with Cuwiring patterns 29P and 29Q, respectively. The lower part of the Cuwiring pattern 29P forms a Cu via plug 29V, which extends through themanganese oxide film 26MOx to make an electrical contact with the Cuwiring pattern 26P.

The side walls of the wiring trenches 28T1 and 28T2 are each coated witha barrier metal film 29BM equivalent to the barrier metal films 23BM and26BM. On the top of the Cu wiring pattern 29P, a manganese oxide film29MOx equivalent to the manganese oxide films 23MOx and 26MOx is formedalong the carbon-including insulating film 30 so as to have a thicknessapproximately in the range of 1 nm to 5 nm. Such a manganese oxide film29MOx is also formed on the top of the Cu wiring pattern 29Q.

The boundary between the Cu wiring pattern 29P and the barrier metalfilm 29BM consists of a manganese oxide film 29MOy that is equivalent tothe manganese oxide films 23MOy and 26MOy and formed so as to have athickness in the range of 1 nm to 5 nm.

In a semiconductor device 40 having the multilayer wiring structure 20configured as above, each of the insulating films 23MOx, 26MOx, and29MOx formed on the Cu wiring patterns 23P and 23Q, 26P to 26R, and 29Pand 29Q, respectively, includes a substantial amount of carbon asdescribed above, and this reduces interatomic distances inside thefilms, thereby providing stronger chemical bonds. As a result, theseinsulating films act as excellent diffusion barriers and effectivelyprevent diffusion of Cu atoms constituting wiring patterns intolow-dielectric-constant interlayer insulating films, thereby avoidingshort circuits and other defects.

Next, a manufacturing process of the semiconductor device 40, inparticular, a process of forming the multilayer wiring structure, isdescribed with reference to FIGS. 5A to 5L and FIG. 6.

In FIG. 5A, the insulating film 43 is formed on the silicon substrate 41so as to cover the transistors Tr1 and Tr2, and then the interlayerinsulating film 22 is formed on the insulating film 43. Examples of thisinterlayer insulating film 22 may include an MSQ film or otherSiO₂-based low-dielectric-constant films formed by a coating method, ahydrocarbon polymer film such as SiLK or Porous SiLK (registeredtrademarks of The Dow Chemical Company), and a SiOC film produced byplasma CVD.

In the next step, the wiring trench 22T1 is carved through theinterlayer insulating film 22 as shown in FIG. 5B. Although not shown inthe drawing, the wiring trench 22T2 is also carved through theinterlayer insulating film 22.

Then, as shown in FIG. 5C, the barrier metal film 23BM is formed on theinterlayer insulating film 22 by sputtering of a Ta film, Ti film, or Wfilm at room temperature so as to have the cross-sectional shape fittingthe wiring trench 22T1 and have a thickness in the range of 2 nm to 5nm. To form this barrier metal film 23BM, reactive sputtering of aconductive nitride film such as a TaN film, TiN film, or WN film undernitrogen atmosphere may be used. The temperature of the substraterequired for sputtering is approximately 400° C. Although not shown inthe drawing, such a barrier metal film 23BM is also formed on the wiringtrench 22T2. In the step shown in FIG. 5C, a Cu—Mn alloy layer 23CM isalso formed on the barrier metal film 23BM by sputtering of Cu—Mn alloyat room temperature. This Cu—Mn alloy layer 23CM includes Mn atoms at aconcentration in the range of

0.2 to 1.0 atomic percent or preferably at a concentration equal to orless than 0.5 atomic percent, has the cross-sectional shape fitting thewiring trench 22T1, and has a thickness in the range of 5 nm to 30 nm.Although not shown in the drawing, such a Cu—Mn alloy layer 23CM is alsoformed on the wiring trench 22T2.

FIG. 5C also includes a Cu layer 23, which is formed on the Cu—Mn alloylayer 23CM by seed layer formation and electrolytic plating so as tofill the wiring trench 22T1 and, although not shown in the drawing, thewiring trench 22T2 as well.

Thereafter, as shown in FIG. 5D, the Cu layer 23, and the Cu—Mn alloylayer 23CM and the barrier metal films 23BM formed therebeneath areshaved by CMP until the surface of the interlayer insulating film 22 isexposed. This results in the formation of the Cu wiring pattern 23P inthe wiring trench 22T1 and, although not shown in the drawing, the Cuwiring pattern 23Q in the wiring trench 22T2.

In this embodiment, the structure obtained in FIG. 5D is then coatedwith the carbon-including insulating film 24 having a thickness in therange of 15 nm to 30 nm as shown in FIG. 5E. The carbon-includinginsulating film 24 used in this embodiment is a SiCN film, which isformed by plasma CVD of a material including Si and C such astrimethylsilane (SiH(CH₃)₃) and a different material including nitrogensuch as NH₃ with the substrate temperature being, for example, in therange of 350 to 400° C. Oxygen is added in the course of forming thecarbon-including insulating film 24 so that the entire film includesoxygen at a concentration in the range of 3 to 18 atomic percent.

During this step shown in FIG. 5E, heat generated by the formation ofthe carbon-including insulating film 24 transports Mn atoms existing inthe Cu—Mn alloy layer 23CM to the surface of the Cu wiring pattern 23Pas shown in FIG. 6. The transported Mn atoms react with Si, carbon, andoxygen atoms supplied by the carbon-including insulating film 24. As aresult, a manganese oxide film 23MOx is formed on the surface of the Cuwiring pattern 23P while spreading along the carbon-including insulatingfilm 24. The manganese oxide film 23MOx formed in this way has acomposition of MnSi_(x)O_(y)C_(z) including composition parameters x, y,and z.

A manganese oxide film 23MOx was actually prepared in the same way andanalyzed by energy dispersive X-ray spectroscopy (EDX). This analysisfound that the composition parameter x was in the range of 0.3 to 1.0, ywas in the range of 0.75 to 3.0, and z was in the range of 0.2 to 0.7.Furthermore, secondary ion mass spectroscopy (SIMS) of a samplestructure wherein a flat Cu—Mn film was coated with a Cu film and the Cufilm was then coated with a SiCN film and the entire structure washeated at a temperature of 400° C. also demonstrated that this method,wherein a SiCN film is formed in contact with a Cu—Mn film, may be usedto provide a manganese oxide film that has a composition ofMnSi_(x)O_(y)C_(z) and spreads between the SiCN and Cu—Mn films.

The step represented by FIG. 5E also involves transportation of a smallnumber of oxygen atoms from the interlayer insulating film 22 throughthe barrier metal film 23BM to the Cu wiring pattern 23P during heattreatment associated with the formation of the carbon-includinginsulating film 24. As shown in FIG. 6, such oxygen atoms react withsome of Mn atoms initially included in the Cu—Mn alloy layer 23CM,thereby producing another manganese oxide film 23MOy between the barriermetal film 23BM and the Cu wiring pattern 23P. This manganese oxide film23MOy includes no or little carbon and Si, and the concentrations ofthese elements included therein are lower than those in the manganeseoxide film 23MOx, if any. Therefore, the manganese oxide film 23MOyproduced in this way has a composition of MnO_(p)C_(q) wherein thecomposition parameter p is in the range of 0.5 to 1.5 and q is in therange of 0.01 to 0.05, as described earlier. It should be noted that qis smaller than z.

The original Cu—Mn alloy layer 23CM is reduced as such manganese oxidefilms 23MOx and 23MOy are formed and finally disappears at the end ofthe step represented by FIG. 5E due to replacement with a Cu layerserving as a part of the Cu wiring pattern 23P.

In the next step shown in FIG. 5F, the structure illustrated by FIG. 5Eis covered with the interlayer insulating film 25 formed in the samemanner as the interlayer insulating film 22. After that, as shown inFIG. 5G, a wiring trench 25T1 and a via hole 25V1 are carved inpreparation for the formation of the Cu wiring pattern 26P, and thisexposes the Cu wiring pattern 23P under the wiring trench 25T1 and thevia hole 25V1. At the same time, the wiring trenches 25T2 and 25T3 arecarved through the interlayer insulating film 25 in preparation for theformation of the Cu wiring patterns 26Q and 26R, respectively.

Then, as shown in FIG. 5H, the barrier metal film 26BM is formed on theinterlayer insulating film 25, which is illustrated in FIG. 5G, bysputtering of a Ta film, Ti film, or W film at room temperature so as tohave the cross-sectional shape fitting the wiring trench 25T1 and has athickness in the range of 2 nm to 5 nm. To form this barrier metal film26BM, reactive sputtering of a conductive nitride film such as a TaNfilm, TiN film, or WN film under nitrogen atmosphere may be used. Thetemperature of the substrate required for sputtering is approximately400° C. Although not shown in the drawing, such a barrier metal film26BM is also formed on the wiring trenches 25T2 and 25T3.

In the step shown in FIG. 5H, a Cu—Mn alloy layer 26CM is also formed onthe barrier metal film 26BM by sputtering of Cu—Mn alloy at roomtemperature. This Cu—Mn alloy layer 26CM includes Mn atoms at aconcentration in the range of 0.2 to 1.0 atomic percent, has thecross-sectional shape fitting the wiring trench 25T1, and has athickness in the range of 5 nm to 30 nm. Although not shown in thedrawing, such a Cu—Mn alloy layer 26CM is also formed on the wiringtrenches 25T2 and 25T3.

FIG. 5H also includes a Cu layer 26, which is formed on the Cu—Mn alloylayer 26CM by seed layer formation and electrolytic plating so as tofill the wiring trench 25T1 and, although not shown in the drawing, thewiring trenches 25T2 and 25T3 as well.

Thereafter, as shown in FIG. 5I, the Cu layer 26, and the Cu—Mn alloylayer 26CM and the barrier metal film 26BM formed therebeneath areshaved by CMP until the surface of the interlayer insulating film 25 isexposed. This results in the formation of the Cu wiring pattern 26P inthe wiring trench 25T1 and, although not shown in the drawing, the Cuwiring patterns 26Q and 26R in the wiring trenches 25T2 and 25T3,respectively.

In this embodiment, the structure obtained in FIG. 5I is then coatedwith the carbon-including insulating film 27 having a thickness in therange of 15 nm to 30 nm as shown in FIG. 5J. The carbon-includinginsulating film 27 used in this embodiment is a SiCN film, which isformed by plasma CVD of a material including Si and C such astrimethylsilane (SiH(CH₃)₃) and a different material including nitrogensuch as NH₃ with the substrate temperature being, for example, in therange of 350 to 400° C. Oxygen is added in the course of forming thecarbon-including insulating film 27 so that the entire film includesoxygen at a concentration in the range of 3 to 18 atomic percent.

During this step shown in FIG. 5J, heat generated by the formation ofthe carbon-including insulating film 27 transports Mn atoms existing inthe Cu—Mn alloy layer 26CM to the surface of the Cu wiring pattern 26Pas described earlier using FIG. 6. The transported Mn atoms react withSi, carbon, and oxygen atoms supplied by the carbon-including insulatingfilm 27. As a result, a manganese oxide film 26MOx having a compositionof MnSi_(x)O_(y)C_(z) is formed on the surface of the Cu wiring pattern26P while spreading along the carbon-including insulating film 27, inthe same manner as the manganese oxide film 23MOx.

The step represented by FIG. 5J also involves transportation of a smallnumber of oxygen atoms from the interlayer insulating film 25 throughthe barrier metal film 26BM to the Cu wiring pattern 26P during heattreatment associated with the formation of the carbon-includinginsulating film 27. As described earlier using FIG. 6, such oxygen atomsreact with some of Mn atoms initially included in the Cu—Mn alloy layer26CM, thereby producing another manganese oxide film 26MOy between thebarrier metal film 26BM and the Cu wiring pattern 26P (via plug 26V) inthe same manner as the manganese oxide film 23MOy. This manganese oxidefilm 26MOy includes no or little carbon and Si, and the concentrationsof these elements included therein are lower than those in the manganeseoxide film 26MOx, if any.

Also in this case, the original Cu—Mn alloy layer 26CM is reduced assuch manganese oxide films 26MOx and 26MOy are formed and finallydisappears at the end of the step represented by FIG. 5J.

In the next step shown in FIG. 5K, the structure illustrated by FIG. 5Jis covered with the interlayer insulating film 28 formed in the samemanner as the interlayer insulating films 22 and 25. Then, the stepsshown in FIGS. 5G to 5J are repeated to carve the wiring trench 28T1through the interlayer insulating film 28, to cover the wiring trench28T1 with the barrier metal film 29BM, and then to fill the wiringtrench 28T1 with the Cu wiring pattern 29P. After that, in the upperpart of the Cu wiring pattern 29P, the manganese oxide film 29MOx isformed in the same manner as the manganese oxide films 23MOx and 26MOxalong a carbon-including insulating film 30 formed as with thecarbon-including insulating film 27. In the boundary between the Cuwiring pattern 29P and the barrier metal film 29BM, the manganese oxidefilm 29MOy is formed in the same manner as the manganese oxide films23MOy and 26MOy.

FIG. 7 shows the result of a time-dependent dielectric breakdown test(TDDB test) conducted using a semiconductor device 40 having themultilayer wiring structure 20 configured as above.

In FIG. 7, “(d) CONVENTIONAL ART” indicates the result obtained using astandard device that was tested as a control of the present embodimentand corresponds to the structure described earlier using FIG. 2. Thisstandard device was configured as follows: the Cu wiring patterns 13Peach having a width of 70 nm were arranged at intervals of 70 nm; thebarrier metal film 13BM had a thickness of 2 nm; and the manganese oxidefilm 13MOx had a thickness of 20 nm and a composition of MnSi_(x)O_(y)wherein the composition parameter x is 0.3 and y is 0.5.

“(c) WITHOUT Mn” in FIG. 7 indicates the result obtained using anotherstandard device tested as a control, which was prepared excluding theformation of the Cu—Mn alloy layer 23CM in the steps shown in FIGS. 5Ato 5E and thus had no manganese oxide film 23MOx on the top of Cu wiringpatterns 23P1 and 23P2 as shown in FIG. 8A. In this standard device, theformation of the manganese oxide films 23MOy, which would have beenformed on the side walls and the bottom of the Cu patterns, wasaccordingly omitted. It should be noted that the components in FIG. 8Athat have already been described above are numbered with the referencenumerals used in the previous explanation to avoid repetition. Forcomparison, this standard device included the interlayer insulatingfilms 22 and 25 having the same composition and the same thickness asthose of the interlayer insulating films 12 and 14 shown in FIG. 2 aswell as a barrier metal film 23BM having the same composition and thesame thickness as the barrier metal film 13BM shown in FIG. 2. The widthand intervals of the Cu wiring patterns 23P1 and 23P2 were the same asthose used in the standard device illustrated in FIG. 2.

“(a) EMBODIMENT 1” in FIG. 7 indicates the result obtained using thedevice that corresponds to Embodiment 1 described earlier and thus Cuwiring patterns 23P1 and 23P2 thereof were formed in the steps describedusing FIGS. 5A to 5F, as illustrated in FIG. 8B. It should be noted thatthe components in FIG. 8B that have already been described above arenumbered with the reference numerals used in the previous explanation toavoid repetition. For comparison, this device included the interlayerinsulating films 22 and 25 having the same composition and the samethickness as those of the interlayer insulating films 12 and 14 shown inFIG. 2 as well as a barrier metal film 23BM having the same compositionand the same thickness as the barrier metal film 13BM shown in FIG. 2.The width and interval of the Cu wiring patterns 23P1 and 23P2 were thesame as those used in the standard device illustrated in FIG. 2. “(b)EMBODIMENT 2” in FIG. 7 indicates the result obtained using Embodiment2, which will be described later.

In this test summarized in FIG. 7, a voltage of 30 V was applied betweenadjacent Cu wiring patterns of each device at a temperature of 150° C.and the time to dielectric breakdown was measured.

The TDDB values on the vertical axis of FIG. 7 have been normalized withrespect to the value for the standard device shown in “(d) CONVENTIONALART.” As is obvious from the graph, the TDDB value of the other standarddevice shown on “(c) WITHOUT Mn” is almost equal to that shown in “(d)CONVENTIONAL ART.” This means that the carbon-including film 24 itselfhas little or no ability to prevent diffusion of Cu atoms.

On the other hand, the TDDB value of the device corresponding toEmbodiment 1 and shown in “(a) EMBODIMENT 1” is more than 12 timeshigher than that of the standard device tested as a control.

Therefore, it may be said that, among others, the manganese oxide film23MOx including carbon exhibits especially high performance inpreventing diffusion of Cu atoms and that the semiconductor device 40configured according to Embodiment 1 so as to have such a manganeseoxide film 23MOx and the equivalents thereof, i.e., manganese oxidefilms 26MOx and 29MOx, acquires a long service life.

FIGS. 9A to 9K are diagrams illustrating a manufacturing process of asemiconductor device according to Embodiment 2. It should be noted thatthe components in FIGS. 9A to 9K that have already been described aboveare numbered with the reference numerals used in the previousexplanation to avoid repetition.

FIG. 9A corresponds to the structure shown in FIG. 5D with the exceptionthat the interlayer insulating film 22 is a low-dielectric-constant SiO₂film resistant to etching of a hydrocarbon polymer film, such as an MSQfilm.

In Embodiment 2, as shown in FIG. 9B, a carbon-including film 31 isformed on the structure illustrated by FIG. 9A so as to cover the top ofthe interlayer insulating film 22 and that of the Cu wiring pattern 23P.This carbon-including film 31 is, for example, a hydrocarbon polymerfilm commercially available under the name of SiLK (registeredtrademarks of The Dow Chemical Company) or a similar film that includescarbon (C) and oxygen, is resistant to heat treatment at a temperaturein the range of 350 to 400° C., and allows selective etching of theinterlayer insulating film 22 existing therebeneath.

Then, the structure shown in FIG. 9B is heated at a temperature in therange of 350 to 400° C. under inert atmosphere or, more typically,nitrogen atmosphere. Thereafter, a manganese oxide film 33MOx whosecomposition is represented using composition parameters s and t(MnO_(s)C_(t)) is formed so as to cover the top of the Cu wiring pattern23P while spreading along the hydrocarbon polymer film 31. Morespecifically, the manganese oxide film 33MOx is formed from Mn atomsinitially included in the Cu—Mn alloy layer 23CM and oxygen and carbonatoms supplied by the hydrocarbon polymer film 31 through the reactionthereof so as to have a thickness in the range of 1 nm to 5 nm. Thecomposition parameters s and t of the manganese oxide film 33MOx formedin this way are 0.75 to 3.0 and 0.2 to 0.7, respectively.

Furthermore, oxygen atoms that are released from the interlayerinsulating film 22 penetrate through the barrier metal film 23BM intothe Cu wiring pattern 23P and then react with Mn atoms existing in theCu—Mn alloy layer 23CM, thereby producing a manganese oxide film 33MOyspreading between the Cu wiring pattern 23P and the barrier metal film23BM. This manganese oxide film 33MOy has a composition representedusing composition parameters u and v (MnO_(u)C_(v)) wherein thecomposition parameter v is zero or any number less than t (v<t).

Embodiment 2 further involves the step shown in FIG. 9D, wherein thecarbon-including film 31 was removed through the process of selectiveetching or ashing so as to expose the interlayer insulating film 22 andthe manganese oxide film 33MOx preferentially.

Subsequently, as shown in FIG. 9E, the structure illustrated by FIG. 9Dis covered with the next interlayer insulating film 25 consisting of anMSQ film or a similar silicon oxide film. After that, a wiring trench25T1 and a via hole 25V1 are carved through the interlayer insulatingfilm 25 so that the Cu wiring pattern 23P is exposed, as shown in FIG.9F.

Furthermore, as shown in FIG. 9G, the interlayer insulating film 25 seenin FIG. 9F is coated with the barrier metal film 26BM and then with theCu—Mn alloy film 26CM in the same manner as the step described usingFIG. 5H so that the coating layers have the cross-sectional shapefitting the wiring trench 25T1.

FIG. 9G also includes a Cu layer 26, which is formed on the Cu—Mn alloylayer 26CM by seed layer formation and electrolytic plating so as tofill the wiring trench 25T1 and the via hole 25V1.

Thereafter, as shown in FIG. 9H, the Cu layer 26, and the Cu—Mn alloylayer 26CM and the barrier metal layer 26BM formed therebeneath areshaved by CMP until the surface of the interlayer insulating film 25 isexposed. This results in the formation of the Cu wiring pattern 26P inthe wiring trench 25T1 and, although not shown in the drawing, the Cuwiring patterns 26Q and 26R in the wiring trenches 25T2 and 25T3,respectively.

In this embodiment, the structure obtained in FIG. 9H is then coatedwith the carbon-including film 32 having the same composition as thecarbon-including film 31 and a thickness in the range of 15 nm to 30 nmas shown in FIG. 9I, and then this structure is heated at a temperaturein the range of 350 to 400° C. This heat treatment makes Mn atomsexisting in the Cu—Mn alloy layer 26CM move to the surface of the Cuwiring pattern 26P and react with carbon and oxygen atoms supplied bythe carbon-including film 32 there as described earlier using FIG. 6. Asa result, a manganese oxide film 36MOx having a composition ofMnO_(s)C_(t) described earlier is formed on the surface of the Cu wiringpattern 26P while spreading along the carbon-including film 32, in thesame manner as the manganese oxide film 33MOx.

The step represented by FIG. 9I also involves transportation of a smallnumber of oxygen atoms from the interlayer insulating film 25 throughthe barrier metal film 26BM to the Cu wiring pattern 26P during the heattreatment. As described earlier using FIG. 6, such oxygen atoms reactwith some of Mn atoms initially included in the Cu—Mn alloy layer 26CM,thereby producing another manganese oxide film 36MOy between the barriermetal film 26BM and the Cu wiring pattern 26P (via plug 26V) in the samemanner as the manganese oxide film 33MOy. This manganese oxide film36MOy includes no carbon or carbon at any concentration lower than thatin the manganese oxide film 36MOx.

Also in this case, the original Cu—Mn alloy layer 26CM is reduced assuch manganese oxide films 36MOx and 36MOy are formed and finallydisappears at the end of the step represented by FIG. 9I.

In the next step shown in FIG. 9J, the structure illustrated by FIG. 9Iis covered with the interlayer insulating film 28 formed in the samemanner as the interlayer insulating films 22 and 25. Then, the stepsshown in FIGS. 9E to 9I are repeated to carve the wiring trench 28T1through the interlayer insulating film 28, to cover the wiring trench28T1 with the barrier metal film 29BM, and then to fill the wiringtrench 28T1 with the Cu wiring pattern 29P. After that, in the upperpart of the Cu wiring pattern 29P, an additional carbon-includinginsulating film is formed in the same manner as the carbon-includingfilm 30, and the manganese oxide film 39MOx is formed in the same manneras the manganese oxide films 33MOx and 36MOx along the additionalcarbon-including film. Between the Cu wiring pattern 29P and the barriermetal film 29BM, the manganese oxide film 39MOy is formed in the samemanner as the manganese oxide films 33MOy and 36MOy. It should be notedthat FIG. 9K represents the structure obtained by removing theadditional carbon-including insulating film after the process describedabove.

The result of the TDDB test conducted using the multilayer wiringstructure prepared in accordance with Embodiment 2 is also shown in FIG.7 as “(b) EMBODIMENT 2.” This test involved a semiconductor deviceequivalent to that shown in FIG. 8B with exceptions that the interlayerinsulating film 25 was formed directly on the interlayer insulating film22 and that the manganese oxide films 33MOx and 33MOy were used insteadof the manganese oxide films 23MOx and 23MOy as shown in FIG. 10. Thisdevice also employed an interval of 70 nm between adjacent Cu wiringpatterns as well as the other tested devices.

As clearly seen in FIG. 7, the TDDB value of the device corresponding toEmbodiment 2 is also more than 12 times higher than that of the standarddevice tested as a control.

Meanwhile, FIG. 11 represents the result of short-circuit study, whereina test structure in which upper Cu wiring patterns 18P extend whilecrossing over the lower Cu wiring patterns 13P, like one describedearlier using FIG. 3F, was prepared through the steps shown in FIGS. 9Ato 9K and then occurrences of short circuits between the upper and lowerCu wiring patterns were monitored. As shown in FIG. 12, this teststructure includes the lower Cu wiring patterns 13P and the upper Cuwiring patterns 18P arranged so as to be perpendicular to each other,and the interval between adjacent Cu wiring patterns was set at 70 nmfor both upper and lower patterns. In addition, the structure used inthis test was configured without the via plugs 26V and 29V.

As seen in FIG. 11, the occurrence rate of short circuits wasapproximately in the range of 2 to 3% in the semiconductor deviceprepared in accordance with Embodiment 2, whereas the occurrence rate ofshort circuits was higher than 85% in the standard device as a controlprepared in the steps shown in FIGS. 3A to 3F. In this standard deviceprepared in the steps shown in FIGS. 3A to 3F, the diffusion barrierfilm 16 had a bump with a height of 30 nm due to the Cu wiring pattern13P and the height of the interlayer insulating film 17 was 300 nm.

The result shown in FIG. 11 probably reflects the fact that the presentembodiment employs a lower interlayer insulating film 22 and a manganeseoxide film 33MOx both resistant to etching and thus no bump is formedafter the hydrocarbon polymer film 31 is removed by dry etching orashing in the step shown in FIG. 9D.

Meanwhile, in the present embodiment, the interlayer insulating films22, 25, and 28 do not always have to consist of an MSQ film. Althoughhaving a higher dielectric constant, a silicon oxide film produced byplasma CVD of tetraethoxysilane (TEOS) may also be used depending on theintended application.

The many features and advantages of the embodiments are apparent fromthe detailed specification and, thus, it is intended by the appendedclaims to cover all such features and advantages of the embodiments thatfall within the true spirit and scope thereof. Further, since numerousmodifications and changes will readily occur to those skilled in theart, it is not desired to limit the inventive embodiments to the exactconstruction and operation illustrated and described, and accordinglyall suitable modification and equivalents may be resorted to, fallingwithin the scope thereof.

1. A method of manufacturing a semiconductor device comprising: forminga first insulating film over a semiconductor substrate; forming a firstopening in the first insulating film; forming a metal film includingmanganese along an inner wall of the first opening; forming a firstcopper wiring in the first opening; planarizing the first insulatingfilm and the first copper wiring; forming a film including carbon overthe first copper wiring; and forming a manganese oxide film includingcarbon over the first copper wiring by performing a heat treatment. 2.The method according to claim 1, wherein the film is a silicon carbidefilm and the silicon carbide film is formed at a temperature in therange from 350° C. to 400° C.
 3. The method according to claim 1,wherein the film is a silicon carbide film and the silicon carbide filmincluding oxygen at a concentration in the range from 3% to 18%.
 4. Themethod according to claim 1, wherein the film is formed by plasmachemical vapor deposition.
 5. The method according to claim 1, furthercomprising forming a second insulating film over the manganese oxidefilm.
 6. The method according to claim 1, further comprising forming asilicon carbide insulating film over the manganese oxide film.
 7. Themethod according to claim 1, further comprising: forming a secondinsulating film over the first insulating film and the manganese oxidefilm; forming a second opening in the second insulating film; andforming a second copper wiring in the second opening; wherein a portionof the manganese oxide film is removed to make an electric contactbetween the first copper wiring and the second copper wiring.
 8. Themethod according to claim 7, further comprising forming ahigh-melting-point metal film along an inner wall of each of the firstopening and the second opening.
 9. The method according to claim 1,further comprising forming a hydrocarbon insulating film over themanganese oxide film as the film.
 10. The method according to claim 9,wherein the hydrocarbon insulating film is removed by etching using a H₂or NH₃ gas.
 11. The method according to claim 1, wherein the film isformed by a coating method.